Flexible, light solar cells could provide new opportunities

MIT researchers have produced a new kind of photovoltaic cell based on sheets of flexible graphene coated with a layer of nanowires. The approach could lead to low-cost, transparent and flexible solar cells that could be deployed on windows, roofs or other surfaces.

The new approach is detailed in a report published in the journal Nano Letters, co-authored by MIT postdocs Hyesung Park and Sehoon Chang, associate professor of materials science and engineering Silvija Gradecak, and eight other MIT researchers.

While most of today’s solar cells are made of silicon, these remain expensive because the silicon is generally highly purified and then made into crystals that are sliced thin. Many researchers are exploring alternatives, such as nanostructured or hybrid solar cells; indium tin oxide (ITO) is used as a transparent electrode in these new solar cells.

“Currently, ITO is the material of choice for transparent electrodes,” Gradecak says, such as in the touch screens now used on smartphones. But the indium used in that compound is expensive, while graphene is made from ubiquitous carbon.

The new material, Gradecak says, may be an alternative to ITO. In addition to its lower cost, it provides other advantages, including flexibility, low weight, mechanical strength and chemical robustness.

Building semiconducting nanostructures directly on a pristine graphene surface without impairing its electrical and structural properties has been challenging due to graphene’s stable and inert structure, Gradecak explains. So her team used a series of polymer coatings to modify its properties, allowing them to bond a layer of zinc oxide nanowires to it, and then an overlay of a material that responds to light waves — either lead-sulfide quantum dots or a type of polymer called P3HT.

Despite these modifications, Gradecak says, graphene’s innate properties remain intact, providing significant advantages in the resulting hybrid material.

“We’ve demonstrated that devices based on graphene have a comparable efficiency to ITO,” she says — in the case of the quantum-dot overlay, an overall power conversion efficiency of 4.2 percent — less than the efficiency of general purpose silicon cells, but competitive for specialized applications. “We’re the first to demonstrate graphene-nanowire solar cells without sacrificing device performance.”

In addition, unlike the high-temperature growth of other semiconductors, a solution-based process to deposit zinc oxide nanowires on graphene electrodes can be done entirely at temperatures below 175 degrees Celsius, says Chang, a postdoc in MIT’s Department of Materials Science and Engineering (DMSE) and a lead author of the paper. Silicon solar cells are typically processed at significantly higher temperatures.

The manufacturing process is highly scalable, adds Park, the other lead author and a postdoc in DMSE and in MIT’s Department of Electrical Engineering and Computer Science. The graphene is synthesized through a process called chemical vapor deposition and then coated with the polymer layers. “The size is not a limiting factor, and graphene can be transferred onto various target substrates such as glass or plastic,” Park says.

Gradecak cautions that while the scalability for solar cells hasn’t been demonstrated yet — she and her colleagues have only made proof-of-concept devices a half-inch in size — she doesn’t foresee any obstacles to making larger sizes. “I believe within a couple of years we could see [commercial] devices” based on this technology, she says.

László Forró, a professor at the Ecole Polytechnique Fédérale de Lausanne, in Switzerland, who was not associated with this research, says that the idea of using graphene as a transparent electrode was “in the air already,” but had not actually been realized.

“In my opinion this work is a real breakthrough,” Forró says. “Excellent work in every respect.”

He cautions that “the road is still long to get into real applications, there are many problems to be solved,” but adds that “the quality of the research team around this project … guarantees the success.”

The work also involved MIT professors Moungi Bawendi, Mildred Dresselhaus, Vladimir Bulovic and Jing Kong; graduate students Joel Jean and Jayce Cheng; postdoc Paulo Araujo; and affiliate Mingsheng Wang. It was supported by the Eni-MIT Alliance Solar Frontiers Program, and used facilities provided by the MIT Center for Materials Science Engineering, which is supported by the National Science Foundation. 

View the original article here

Tiny compound semiconductor transistor could challenge silicon’s dominance

Silicon’s crown is under threat: The semiconductor’s days as the king of microchips for computers and smart devices could be numbered, thanks to the development of the smallest transistor ever to be built from a rival material, indium gallium arsenide.

The compound transistor, built by a team in MIT’s Microsystems Technology Laboratories, performs well despite being just 22 nanometers (billionths of a meter) in length. This makes it a promising candidate to eventually replace silicon in computing devices, says co-developer Jesús del Alamo, the Donner Professor of Science in MIT’s Department of Electrical Engineering and Computer Science (EECS), who built the transistor with EECS graduate student Jianqian Lin and Dimitri Antoniadis, the Ray and Maria Stata Professor of Electrical Engineering.

To keep pace with our demand for ever-faster and smarter computing devices, the size of transistors is continually shrinking, allowing increasing numbers of them to be squeezed onto microchips. “The more transistors you can pack on a chip, the more powerful the chip is going to be, and the more functions the chip is going to perform,” del Alamo says.

But as silicon transistors are reduced to the nanometer scale, the amount of current that can be produced by the devices is also shrinking, limiting their speed of operation. This has led to fears that Moore’s Law — the prediction by Intel founder Gordon Moore that the number of transistors on microchips will double every two years — could be about to come to an end, del Alamo says.

To keep Moore’s Law alive, researchers have for some time been investigating alternatives to silicon, which could potentially produce a larger current even when operating at these smaller scales. One such material is the compound indium gallium arsenide, which is already used in fiber-optic communication and radar technologies, and is known to have extremely good electrical properties, del Alamo says. But despite recent advances in treating the material to allow it to be formed into a transistor in a similar way to silicon, nobody has yet been able to produce devices small enough to be packed in ever-greater numbers into tomorrow’s microchips.

Now del Alamo, Antoniadis and Lin have shown it is possible to build a nanometer-sized metal-oxide semiconductor field-effect transistor (MOSFET) — the type most commonly used in logic applications such as microprocessors — using the material. “We have shown that you can make extremely small indium gallium arsenide MOSFETs with excellent logic characteristics, which promises to take Moore’s Law beyond the reach of silicon,” del Alamo says.

Transistors consist of three electrodes: the gate, the source and the drain, with the gate controlling the flow of electrons between the other two. Since space in these tiny transistors is so tight, the three electrodes must be placed in extremely close proximity to each other, a level of precision that would be impossible for even sophisticated tools to achieve. Instead, the team allows the gate to “self-align” itself between the other two electrodes.

The researchers first grow a thin layer of the material using molecular beam epitaxy, a process widely used in the semiconductor industry in which evaporated atoms of indium, gallium and arsenic react with each other within a vacuum to form a single-crystal compound. The team then deposits a layer of molybdenum as the source and drain contact metal. They then “draw” an extremely fine pattern onto this substrate using a focused beam of electrons — another well-established fabrication technique known as electron beam lithography.

Unwanted areas of material are then etched away and the gate oxide is deposited onto the tiny gap. Finally, evaporated molybdenum is fired at the surface, where it forms the gate, tightly squeezed between the two other electrodes, del Alamo says. “Through a combination of etching and deposition we can get the gate nestled [between the electrodes] with tiny gaps around it,” he says.

Although many of the techniques applied by the team are already used in silicon fabrication, they have only rarely been used to make compound semiconductor transistors. This is partly because in applications such as fiber-optic communication, space is less of an issue. “But when you are talking about integrating billions of tiny transistors onto a chip, then we need to completely reformulate the fabrication technology of compound semiconductor transistors to look much more like that of silicon transistors,” del Alamo says.

The team presents its work this week at the International Electron Devices Meeting in San Francisco.

Their next step will be to work on further improving the electrical performance — and hence the speed — of the transistor by eliminating unwanted resistance within the device. Once they have achieved this, they will attempt to further shrink the device, with the ultimate aim of reducing the size of their transistor to below 10 nanometers in gate length.

Matthias Passlack, of Taiwanese semiconductor manufacturer TSMC, says del Alamo’s work has been a milestone in semiconductor research. “He and his team have experimentally proven that indium arsenide channels outperform silicon at small-device dimensions,” he says. “This pioneering work has stimulated and facilitated the development of CMOS-compatible, III-V-based-technology research and development worldwide.” 

View the original article here